Although applicable in principle to any desired integrated circuits, the present invention and also the problem area on which it is based are explained with regard to integrated memory circuits in silicon technology.
Although applicable to any desired trench capacitors having an insulation collar, the present invention and also the problem area on which it is based are discussed with reference to a trench capacitor having an insulation collar for use in a semiconductor memory cell.
In trench capacitors, the doped crystalline silicon of the substrate has previously been utilized as a bottom capacitor electrode layer. More recently it has been proposed to use a metallic bottom capacitor electrode layer as a separate layer in the trench. The following integration variants, in particular, are taken into consideration in this context:                a) deposition of a thin metallic capacitor electrode layer in the trench and subsequent patterning by means of lithography/etching,        b) salicide process, i.e. deposition of a metallic capacitor electrode layer in the trench, which layer comprises an elementary metal, such as e.g. W, Ti, . . . , and subsequent siliciding. This process can be carried out in a self-aligned manner with respect to the insulation collar made of silicon oxide and is described for example in EP 1 364 373 A1.        
What has proved to be problematic in producing a bottom metallic capacitor electrode layer for a trench capacitor is the fact that the bottom metallic capacitor electrode layer must be very thin, on the one hand, in order not to greatly reduce the area of the trench capacitor and, on the other hand, the integration requires conventional lithography and etching processes which complicate the method sequence and which have structural limitations.